Dynamic random access memory (DRAM) arrays include memory cells comprising of a storage capacitor and an access transistor. Any data to be read out from the memory cells requires sense amplifier circuits to provide a logic state corresponding to the charge stored in the storage capacitor of the memory cells. Performance of the DRAM can be affected by the speed at which this data is sensed.
While traditional DRAM bitline precharge schemes precharge bitlines to a mid-point voltage level, such schemes restrict sensing performance/speed when the internal high voltage supply (VDD) is too low, or the operating temperature is too low or negative. Hence a precharge to VDD or VSS scheme can be used instead. FIG. 1 illustrates a typical precharge to VDD scheme for DRAM. This precharge to VDD scheme uses reference cells that are similar to normal memory cells.
FIG. 1 is a circuit schematic showing a pair of complementary bitlines and memory cells of a typical DRAM memory array, and the core circuits involved for sensing the memory cell data. Connected to each of the complementary bitlines are memory cells, one of which is outlined in a dashed box referred to by reference number 10. Each DRAM memory cell includes an access transistor 12 in series with a storage capacitor 14. Access transistor 12 has its gate terminal connected to a wordline WL0 and the other terminal of storage capacitor 14 is connected to a cell plate voltage VCP. Those skilled in the art will understand that each memory cell connected to complementary bitlines BLi and BLi_b will be connected to a different wordline.
The sense circuitry for complementary bitlines BLi and BLi_b will now be described. Connected to each bitline are reference cells, one of which is outlined in a dashed box referred to by reference number 16. The function of the reference cells is to provide a reference voltage, slightly different from VDD, to either BLi or BLi_b. Those skilled in the art will understand that the reference voltage is applied to the unaccessed bitline, which depends on the particular wordline that is activated. Each reference memory cell is preferably identical in construction to a normal memory cell 10. Reference cell 16 includes an access transistor 18 in series with a storage capacitor 20. The gate terminal of access transistor 18 is connected to reference wordline RWL. Accordingly, the gate terminal of the other reference cell access transistor is connected to a different reference wordline RWL_b. Persons skilled in the art will understand that the wordlines and the reference wordlines can be logically decoded as being odd or even wordlines. Gating devices 22 and 24 couple a reference voltage VREF (ie. mid-point voltage level) to the storage capacitors of both reference cells in response to enable signal LOAD.
A bitline precharge circuit consisting of p-channel transistors 26 and 28 connected in series between BLi and BLi_b couple supply voltage VDD thereto in response to equalize signal BLEQ. When activated, BLEQ is driven to ground. A standard CMOS cross-coupled inverter sense amplifier consisting of transistors 30, 32, 34 and 36 senses a voltage differential between BLi and BLi_b. The n-channel devices receive a controlled low voltage level supply SN, where SN enables sensing functionality of the sense amplifier. The common node of transistors 30 and 32 are connected to VDD. Finally, a pair of column select devices 38 and 40 can couple BLi and BLi_b to respective global datalines GBLi and GBLi_b in response to column select signal YSEL.
The general sensing operation of the circuit of FIG. 1 is as follows. First, the bitlines are precharged to VDD by driving BLEQ to the low logic level during a precharge period. During this time signal LOAD is driven to the active level to couple VREF to the storage capacitors of both reference memory cells. VREF can be a mid-VDD voltage level for example. SN remains at VDD during the precharge period to disable the bitline sense amplifier.
During an active period, BLEQ is driven to the high logic level to turn off transistors 26 and 28, and enable signal LOAD is driven to the high logic level to turn off transistors 22 and 24. A wordline is driven to the active low logic level to couple its storage capacitor to a bitline. In this example, WL0 is activated. If storage capacitor 14 stores a logic “1” charge, then its stored charge will not change the voltage level of BLi. On the other hand, if storage capacitor 14 stores a logic “0”, the voltage level of BLi is reduced through charge sharing. Through proper decoding, the reference charge of the memory cell connected to the complementary bitline BLi_b will be transferred to BLi_b by activating RWL_b when WL0 is activated. Because the reference storage capacitor 14 stores about half the charge of a logic “1” in a normal memory cell, the voltage level of BLi_b will drop. Then SN is driven to a low voltage level to enable the bitline sense amplifier and sense the voltage difference between BLi and BLi_b. When the full logic levels have been established by the bitline sense amplifier on BLi and BLi_b, YSEL can be activated to couple BLi and BLi_b to the global datalines GBL and GBL_b.
There are disadvantages associated in using reference cells for providing the reference voltage VREF for sensing. The reference cells and associated reference voltage circuits are additional devices within the memory array area, thereby increasing the size of the memory array. Since each reference cell provides a reference voltage to the complementary bitline, there can be variations in the reference voltage provided by different reference cells. This is mainly due to the fact that the reference cells are fabricated in a pitch of memory cells to be similar to the normal memory cells. Hence they will have a small size and be sensitive to process variations.
It is, therefore, desirable to provide a DRAM bitline precharge scheme that does not occupy additional memory array area, while providing the same reference voltage to all the unaccessed bitlines during a read operation.